To allow low-cost memories and high-performance logic products with large embedded memory blocks, Stanford University's Nanofabrication Facility (SNF) along with Daejeon, Korea-based National NanoFab centre (NNFC) and Oregon-based BeSang are reporting what they say is a 3D IC technology breakthrough.
This technology forms full 3D interconnects below and above the vertical devices, whereas conventional semiconductor technologies contain planar devices on the surface of the semiconductor substrate and interconnects only above the planar devices.
Stanford University Professor and head of SNF, Dr. Dr. Yoshio Nishi explained in a statement, "One of unique features of BeSang's 3D IC is the capability of unrestricted 3D interconnections using conventional via technologies that does not require wafer alignment nor through-silicon vias for 3D interconnects. Conventional CMOS technology is facing its scaling limits. Therefore, this emerging 3D IC technology will extend the lifespan of CMOS technology, because it is an excellent alternative way to accommodate more devices on a given wafer area."
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