Figure 1.  Diagram for a Tri-State Output Circuit

Digital circuits often use circuit paths and nodes that are shared by different IC's connected to them.  For example, memory chips share the same data buses to send and receive data from other chips.  There is, therefore, a need to let these chips share data systematically so that no data clashes ever occur on any bus, i.e., no conflicting data are put on the same bus at the same time. This is achieved by employing what is known as the tri-state output.

A tri-state output is basically an output that can assume three states: logic '1', logic '0', and a high-impedance state. The '1' and '0' states are of course used to represent real output data on a shared bus.  An output that is in a high-impedance state, as its name implies, is simply one that is electrically isolated from the bus.

The circuit in Figure 1 shows how a digital tri-state output circuit may be implemented. If the 'enable' pin is at logic '0', the base-emitter and base-collector junctions of both Q1 and Q2 are reverse-biased regardless of what the input's logic state is, which prevent base currents from flowing in both Q3 and Q4. This effectively turns off Q3 and Q4, putting the output pin in high-impedance mode.

If the 'enable' pin is at logic '1' and the input is at logic '0', Q2 conducts and pulls Q4's base voltage to '0', causing Q4 to conduct. At the same time, Q1 cuts off and prevents Q3 from turning 'on'. With Q3 'off' and Q4 conducting,  the output is pulled to ground.  In short, the logic '0' at the input appears at the output.

If the 'enable' pin is at logic '1' and the input is at logic '1', Q2 turns off which also turns off Q4. At the same time, Q1 conducts and causes current to flow into Q3's base, turning it 'on'. With Q3 'on' and Q4 'off',  the output is pulled to +5V.  In short, the logic '1' at the input appears at the output.

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