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PCI Bus Signals

 

 

 
 

         

The Peripheral Component Interconnect, or PCI, is a standard high-speed computer bus for attaching peripheral devices, such as network controllers, graphics cards, sound cards, and the like, to a computer.  The PCI is 32 bits wide, but actually functions like a 64-bit bus.  It is processor-independent and is actually used by both PC's and non-PC's alike.  Table 1 shows the signals of a PCI bus. See More Reference Tables.

   

 

Table 1.  PCI Bus Signals

Pin #

PCI Signal

Pin #

PCI Signal

Pin #

PCI Signal

Pin #

PCI Signal

A1

Test Logic Reset

A47

Address/Data 11

B1

-12 VDC

B47

Address/Data 12

A2

+12 VDC

A48

Ground

B2

Test Clock

B48

Address/Data 10

A3

Test Mode Select

A49

Address/Data 9

B3

Ground

B49

Ground

A4

Test Data Input

A50

Ground or Open

B4

Test Data Output

B50

Ground or Open

A5

+5 VDC

A51

Ground or Open

B5

+5 VDC

B51

Ground or Open

A6

Interrupt A

A52

Command Byte Enable 0

B6

+5 VDC

B52

Address/Data 8

A7

Interrupt C

A53

+3.3 VDC

B7

Interrupt B

B53

Address/Data 7

A8

+5 VDC

A54

Address/Data 6

B8

Interrupt D

B54

+3.3 VDC

A9

Reserved

A55

Address/Data 4

B9

Present

B55

Address/Data 5

A10

Power (+5/3.3 V)

A56

Ground

B10

Reserved

B56

Address/Data 3

A11

Reserved

A57

Address/Data 2

B11

Present

B57

Ground

A12

Ground or Open

A58

Address/Data 0

B12

Ground or Open

B58

Address/Data 1

A13

Ground or Open

A59

Power (+5/3.3 V)

B13

Ground or Open

B59

Power (+5/3.3 V)

A14

-----

A60

Request 64 bit

B14

Reserved

B60

Ack 64-bit

A15

Reset

A61

+5 VDC

B15

Ground

B61

+5 VDC

A16

Power (+5/3.3 V)

A62

+5 VDC

B16

Clock

B62

+5 VDC

A17

Grant PCI use

A63

Ground

B17

Ground

B63

Reserved

A18

Ground

A64

Command Byte Enable 7

B18

Request

B64

Ground

A19

Pwr Mgt Event

A65

Command, Byte Enable 5

B19

Power (+5 V or +3.3 V)

B65

Command Byte Enable 6

A20

Address/Data 30

A66

Power (+5 V or +3.3 V)

B20

Address/Data 31

B66

Command, Byte Enable 4

A21

+3.3 VDC

A67

Parity 64

B21

Address/Data 29

B67

Ground

A22

Address/Data 28

A68

Address/Data 62

B22

Ground

B68

Address/Data 63

A23

Address/Data 26

A69

Ground

B23

Address/Data 27

B69

Address/Data 61

A24

Ground

A70

Address/Data 60

B24

Address/Data 25

B70

Power (+5/3.3 V)

A25

Address/Data 24

A71

Address/Data 58

B25

+3.3VDC

B71

Address/Data 59

A26

Initialization Device Select

A72

Ground

B26

Command Byte Enable 3

B72

Address/Data 57

A27

+3.3 VDC

A73

Address/Data 56

B27

Address/Data 23

B73

Ground

A28

Address/Data 22

A74

Address/Data 54

B28

Ground

B74

Address/Data 55

A29

Address/Data 20

A75

Power (+5/3.3 V)

B29

Address/Data 21

B75

Address/Data 53

A30

Ground

A76

Address/Data 52

B30

Address/Data 19

B76

Ground

A31

Address/Data 18

A77

Address/Data 50

B31

+3.3 VDC

B77

Address/Data 51

A32

Address/Data 16

A78

Ground

B32

Address/Data 17

B78

Address/Data 49

A33

+3.3 VDC

A79

Address/Data 48

B33

Command Byte Enable 2

B79

Power (+5/+3.3 V)

A34

Frame

A80

Address/Data 46

B34

Ground

B80

Address/Data 47

A35

Ground

A81

Ground

B35

Initiator Ready

B81

Address/Data 45

A36

Target Ready

A82

Address/Data 44

B36

+3.3 VDC

B82

Ground

A37

Ground

A83

Address/Data 42

B37

Device Select

B83

Address/Data 43

A38

Stop X'fer Cycle

A84

Power (+5/3.3 V)

B38

Ground

B84

Address/Data 41

A39

+3.3 VDC

A85

Address/Data 40

B39

Lock bus

B85

Ground

A40

Snoop Done

A86

Address/Data 38

B40

Parity Error

B86

Address/Data 39

A41

Snoop Back-off

A87

Ground

B41

+3.3 VDC

B87

Address/Data 37

A42

Ground

A88

Address/Data 36

B42

System Error

B88

Power (+5/+3.3 V)

A43

Parity

A89

Address/Data 34

B43

+3.3 VDC

B89

Address/Data 35

A44

Address/Data 15

A90

Ground

B44

Command Byte Enable 1

B90

Address/Data 33

A45

+3.3 VDC

A91

Address/Data 32

B45

Address/Data 14

B91

Ground

A46

Address/Data 13

A93

Ground

B46

Ground

B94

Ground